rev 2.0 ?2012 advanced linear devices, inc. 415 tasman drive, sunnyvale, ca 94089-1706 tel: (408) 747-1155 fax: (408) 747-1286 www.aldinc.com ald1103 a dvanced l inear d evices, i nc. dual n-channel and dual p-channel matched mosfet pair general description the ald1103 is a monolithic dual n-channel and dual p-channel matched transistor pair intended for a broad range of analog applications. these enhancement-mode transistors are manufactured with advanced linear devices' enhanced acmos silicon gate cmos process. it consists of an ald1101 n-channel mosfet pair and an ald1102 p-channel mosfet pair in one package. the ald1103 offers high input impedance and negative current temperature coefficient. the transistor pair is matched for minimum offset voltage and differential thermal response, and it is designed for precision signal switching and amplifying applications in +2v to +12v systems where low input bias current, low input capacitance and fast switching speed are desired. since these are mosfet devices, they feature very large (almost infinite) current gain in a low frequency, or near dc, operating environment. when used in pairs, a dual cmos analog switch can be constructed. in addition, the ald1103 is intended as a building block for differential amplifier input stages, transmission gates, and multiplexer applications. the ald1103 is suitable for use in precision applications which require very high current gain, beta, such as current mirrors and current sources. the high input impedance and the high dc current gain of the field effect transistors result in extremely low current loss through the control gate. the dc current gain is limited by the gate input leakage current, which is specified at 50pa at room temperature. for example, dc beta of the device at a drain current of 5ma at 25 c is = 5ma/50pa = 100,000,000. features ? thermal tracking between n-channel and p-channel pairs ? low threshold voltage of 0.7v for both n-channel & p-channel mosfets ? low input capacitance ? low vos -- 10mv ? high input impedance -- 10 13 w typical ? low input and output leakage currents ? negative current (i ds ) temperature coefficient ? enhancement mode (normally off) ? dc current gain 10 9 ? matched n-channel and matched p-channel in one package ? rohs compliant pin configuration applications ? precision current mirrors ? complementary push-pull linear drives ? analog switches ? choppers ? differential amplifier input stage ? voltage comparator ? data converters ? sample and hold ? analog inverter ? precision matched current sources dn2 gn2 sn2 gp2 sp2 gn1 sn1 dp1 gp1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 dn1 v + v - dp2 sp1 block diagram n source 1 (3) substrate (4) n source 2 (12) n gate 2 (13) n drain 1 (1) n gate 1 (2) n drain 2 (14) p source 1 (7) substrate (11) p source 2 (8) p gate 2 (9) p drain 1 (5) p gate 1 (6) p drain 2 (10) top view sbl, pbl, db packages operating temperature range* 0 c to +70 c0 c to +70 c -55 c to +125 c 14-pin 14-pin 14-pin small outline plastic dip cerdip package (soic) package package ALD1103SBL ald1103pbl ald1103db ordering information (l suffix denotes lead-free (rohs)) * contact factory for leaded (non-rohs) or high temperature versions.
ald1103 advanced linear devices 2 of 9 drain-source voltage, v ds 10.6v gate-source voltage, v gs 10.6v power dissipation 500mw operating temperature range sbl, pbl packages 0 c to +70 c db package -55 c to +125 c storage temperature range -65 c to +150 c lead temperature, 10 seconds +260 c caution: esd sensitive device. use static control procedures in esd controlled environment. absolute maximum ratings gate threshold v t 0.4 0.7 1.0 v i ds = 10 m a v gs = v ds -0.4 -0.7 -1.2 v i ds = -10 m a v gs = v ds voltage offset voltage v os 10 mv i ds = 100 m a v gs = v ds 10 mv i ds = -100 m a v gs = v ds v gs1 - v gs2 gate threshold temperature tc vt -1.2 mv/ c -1.3 mv/ c drift on drain i ds (on) 25 40 ma v gs = v ds = 5v -8 -16 ma v gs = v ds = -5v current trans-. g fs 5 10 mmho v ds = 5v i ds = 10ma 2 4 mmho v ds = -5v i ds = -10ma conductance mismatch d g fs 0.5 % 0.5 % output g os 200 m mho v ds = 5v i ds = 10ma 500 m mho v ds = -5v i ds = -10ma conductance drain source r ds(on) 50 75 w v ds = 0.1v v gs = 5v 180 270 w v ds = -0.1v v gs = -5v on resistance drain source on resistance d r ds(on) 0.5 % v ds = 0.1v v gs = 5v 0.5 % v ds = -0.1v v gs = -5v mismatch drain source breakdown bv dss 12 v i ds = 10 m a v gs =0v -12 v i ds = -10 m a v gs =0v voltage off drain i ds(off) 0.1 4 na v ds =12v i gs = 0v 0.1 4 na v ds = -12v v gs = 0v current 4 m at a = 125 c4 m at a = 125 c gate leakage i gss 150pa v ds = 0v v gs =12v 1 50 pa v ds = 0v v gs =-12v current 10 na t a = 125 c10nat a = 125 c input c iss 610pf 610pf capacitance operating electrical characteristics t a = 25 c unless otherwise specified n - channel test p - channel test parameter symbol min typ max unit conditions min typ max unit conditions
ald1103 advanced linear devices 3 of 9 typical p-channel performance characteristics output characteristics drain - source voltage (v) drain - source current (ma) -80 -60 -40 -20 0 v bs = 0v t a = 25 c -10v -8v -6v -4v -2v 0-8 -2 -6 -4 -10 -12 v gs = -12v low voltage output characteristics drain -source voltage (mv) drain-source current (ma) -320 -160 0 160 320 -4 4 2 0 -2 -4v v gs = -12v -6v v bs = 0v t a = 25 c -2v -12 forward transconductance vs. drain - source voltage drain - source voltage (v) 0-8 -2 -6 -4 -10 forward transconductance ( mho) 10000 5000 2000 1000 500 200 100 v bs = 0v f = 1khz i ds = -5ma t a = +125 c t a = +25 c i ds = -1ma transfer characteristic with substrate bias gate - source voltage (v) 0 -0.8 -1.6 -2.4 -3.2 -4.0 -20 -15 -10 -5 0 drain-source current ( a) v bs = 0v 4v 6v 8v 10v 12v v gs = v ds t a = 25 c 2v gate - source voltage (v) r ds (on) vs. gate - source voltage drain - source on resistance ( ) 10000 1000 100 10 -2 0 -4 -6 -8 -10 -12 v ds = 0.4v v bs = 0v t a = +125 c t a = +25 c off drain - current vs. temperature temperature ( c) off - drain source current (a) -50 -25 +25 +50 +75 +125 +100 0 -10 x 10 -6 v ds = -12v v gs = v bs = 0v -10 x 10 -12 -10 x 10 -9
ald1103 advanced linear devices 4 of 9 typical n-channel performance characteristics output characteristics drain -source current (ma) 160 120 80 0 40 v bs = 0v t a = 25 c v gs = 12v 10v 8v 6v 4v 2v drain-source voltage (v) 02 4 681012 low voltage output characteristics drain -source voltage (mv) drain-source current (ma) -160 -80 0 80 160 -8 8 4 0 -4 4v v gs = 12v 6v v bs = 0v t a = 25 c 2v forward transconductance ( mho) forward transconductance vs. drain-source voltage drain -source voltage (v) 1 x10 5 5 x10 4 1 x10 4 5 x10 3 2 x10 3 2 x10 4 1 x10 3 t a = +125 c t a = +25 c i ds = 10ma i ds = 1ma 02 4 681012 v bs = 0v f = 1khz gate - source voltage (v) transfer characteristic with substrate bias drain-source current ( a) 20 15 10 5 0 0 0.8 1.6 2.4 3.2 4.0 v bs = 0v -2v -4v -6v -8v -10v -12v v gs = v ds t a = 25 c gate source voltage (v) r ds (on) vs. gate - source voltage drain - source on resistance ( ) 10000 1000 100 10 2 0 4 6 8 10 12 v ds = 0.2v v bs = 0v t a = +25 c t a = +125 c off drain - current vs. temperature temperature ( c) off - drain source current (a) -50 -25 +25 +50 +75 +125 +100 0 10 x 10 -6 v ds = +12v v gs = v bs = 0v 10 x 10 -12 10 x 10 -9
ald1103 advanced linear devices 5 of 9 differential amplifier current source multiplication current source mirror current source with gate control typical applications i set r set q 3 v + = +5v i source q 1 , q 2 : n - channel mosfet q 3 , q 4 : p - channel mosfet i source = i set = v + -vt r set = 4 r set ~ q 1 q 2 v + = +5v q 4 ald1103 v + pmos pair q 4 v out v in - nmos pair q 2 q 1 v in + current source q 3 q 1 , q 2 : n - channel mosfet q 3 , q 4 : p - channel mosfet ald1103 q set, q 1 ..q n : ald 1101 or ald 1103 n - channel mosfet i set v + = +5v i source = i set x n r set q 2 q 3 q set q 1 q n v + = +5v q 4 i source r set q 1 q 3 i set on off digital logic control of current source q 1 : n - channel mosfet q 3, q 4 : p - channel mosfet 1/2 ald1103 1/4 ald1103
ald1103 advanced linear devices 6 of 9 cascode current sources basic current sources p-channel current source n-channel current source typical applications (cont.) i source v + = +5v r set i set 1 2 3 q 1 5 6 8 q 2 7 i source = i set = v + - vt r set = v + - 1.0 r set q 1, q 2 : n - channel mosfet 1/2 ald1103 ~ = 4 r set ~ v + = +5v 2 3 5 6 7 8 q 4 i source q 3 r set i set 1/2 ald1103 q 3 , q 4 : p - channel mosfet i set v + = +5v q 2 i source r set q 3 q 1 q 1 , q 2 , q 3 , q 4 : n - channel mosfet (ald1101 or ald1103) q 4 i set v + = +5v q 1 q 3 q 2 q 4 i source q1, q2, q3, q4: p - channel mosfet (ald1102 or ald1103) i source = i set = v + - 2vt r set = 3 r set ~ r set
ald1103 advanced linear devices 7 of 9 millimeters inches min max min max dim a a 1 b c d-14 e e h l s 1.75 0.25 0.45 0.25 8.75 4.05 6.30 0.937 8 0.50 0.053 0.004 0.014 0.007 0.336 0.140 0.224 0.024 0 0.010 0.069 0.010 0.018 0.010 0.345 0.160 0.248 0.037 8 0.020 1.27 bsc 0.050 bsc 1.35 0.10 0.35 0.18 8.55 3.50 5.70 0.60 0 0.25 14 pin plastic soic package soic-14 package drawing e d e a a 1 b s (45 ) l c h s (45 )
ald1103 advanced linear devices 8 of 9 14 pin plastic dip package pdip-14 package drawing b 1 d s b e a 2 a 1 a l e e 1 c e 1 millimeters inches min max min max dim a a 1 a 2 b b 1 c d-14 e e 1 e e 1 l s-14 3.81 0.38 1.27 0.89 0.38 0.20 17.27 5.59 7.62 2.29 7.37 2.79 1.02 0 5.08 1.27 2.03 1.65 0.51 0.30 19.30 7.11 8.26 2.79 7.87 3.81 2.03 15 0.105 0.015 0.050 0.035 0.015 0.008 0.680 0.220 0.300 0.090 0.290 0.110 0.040 0 0.200 0.050 0.080 0.065 0.020 0.012 0.760 0.280 0.325 0.110 0.310 0.150 0.080 15
ald1103 advanced linear devices 9 of 9 e e 1 c e 1 d s b 1 e b l a l 2 a 1 l 1 a a 1 b b 1 c d-14 e e 1 e e 1 l l 1 l 2 s 3.55 1.27 0.97 0.36 0.20 -- 5.59 7.73 3.81 3.18 0.38 -- 0 5.08 2.16 1.65 0.58 0.38 19.94 7.87 8.26 5.08 -- 1.78 2.49 15 millimeters inches min max min max dim 0.140 0.050 0.038 0.014 0.008 -- 0.220 0.290 0.150 0.125 0.015 -- 0 0.200 0.085 0.065 0.023 0.015 0.785 0.310 0.325 0.200 -- 0.070 0.098 15 2.54 bsc 7.62 bsc 0.100 bsc 0.300 bsc 14 pin cerdip package cerdip-14 package drawing
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